MICS6000Q VLSI Design Optimization and Closure – Spring 2023


Lecture: Wednesday 13:30-16:20
Venue: E4-201
Instructor: Prof. Yuzhe Ma yuzhema@ust.hk
Office Hours: Monday 16:30 – 17:30 @W4-511

Announcements

  • Feb. 05, 2023: Course webpage is built up and the teaching schedule is online.

Description

This course will introduce fundamental methodologies for VLSI design optimization and design closure. It will cover various topics for improving the VLSI design in many aspects, including performance optimization, power analysis and modeling, timing analysis and closure, physical verification, yield optimization, etc. Students will learn how the design objectives are achieved through different design methodologies and optimizations. Guest lecturer(s) from academia and industry will be invited to provide practical views and supplementary insights.

Prerequisites

Course Requirements

Schedule

Date Topic Reading Note
Feb. 08 L01 Introduction
Feb. 15 L02 Design Constraints
Feb. 22 L03 Timing Analysis
Mar. 01 L04 Timing-driven Design
Mar. 08 L05 Power Modeling and Analysis
Mar. 15 L06 Power Optimization
Mar. 22 L07 Datapath
Mar. 29 L08 Datapath-aware Design
Apr. 05 N/A Qingming Festival
Apr. 12 L09 Physical Verification
Apr. 19 L10 Process Variation and Yield
Apr. 26 L11 Packaging
May  03 L12 Guest Lecture
May  10 Final Presentation


References